Quotation for the modification of INO RPC-DAQ Board-Closing date extension attached

India-based Neutrino Observatory (INO) a multi-institutional mega basic science project.

 The experiment  is to determine neutrino using  about  30,000  large  area  particle  detectors  called  Resistive  Plate  Chambers (RPCs). The data produced by the RPCs  is  recorded  through  about  4  million  high  speed  electronics  channels.  The experiment will be built in a large cavern located inside a mountain near Madurai.

 RPCDAQ  module  is  heart  of  the  data  acquisition  scheme  of  the  ICAL  experiment and is present on each RPC.  The module receives 128 differential signals from the front-end and produces signals required by the back-end electronics as well implements data transfer interface. The module  needs  to  be  implemented  on  a  right-angled  triangular  shaped  board whose sides are of about 125mm in length. Height of the module with components mounted will be about 25mm.

 Complete  design  schematics  along  with  detailed  information  about  the  restrictions  on  modules dimensions,  technical  and  dimensional  details  of  the  chips  and  connectors,  suggestions  on components placement and orientation will be provided. Quotations for module design, production modules, assembly and testing of the modules are being invited. 

Technical requirements:

Technical requirements for modifying the existing INO-RPC-DAQ board are as following:

Customer is looking for building few prototypes boards capable of establishing  communication link using 10 Gbps Passive Optical Network for the India-based Neutrino Observatory, using Kintex XC7K160T with FBG676 package and an optical interface (SFP+ Transceiver Module) mounted on GTX transceiver block of the FPGA.

Customer has schematics with an Altera+Wiznet+RJ45, which needs to be modified before layout. The technical requirement has been divided into three parts, which are described below.

Mechanical Requirements:

 Mechanical dimensions. Vendor will be provided with the mechanical design of the board, which must be followed.

 Thermal management (no active cooling) at board level.

Hardware Requirements:

Replace Altera FPGA with the Kintex 7 (KC160T) FPGA.

b)    Change from linear regulators to switching regulators.

c)    Signal integrity (we will have LVDSsignals coming in and going out), and a TDC chip.

d)    Replace Wiznet+RJ45 (Ethernet MAC &Phy) with optical module (Small form-factor pluggable transceiver).

Software Requirements:

a)    Customer needs an IP for implementing 10 Gbps Passive Optical Network over FPGA with real time data.

b)    The vendor needs to provide Tcl or Rtl coding of the IP.

c)    IP needs to flexible enough to be integrated with any other IPs for same device.