RTL Verification for Project Coordination

Call for services required for research project coordination and Training curriculum development in the areas of Bluespec RTL Design, Verification and FPGA optimization.Should have expertise in High Assurance Boot Architectures, Processor Design and High level HDL (Bluespec or CHISEL).

Reference: 
CSEN/2013/009/KAMA/SPLX
Opening Date: 
21/01/14
Closing Date: 
05/02/14
Address: 
Prof. V. Kamakoti, Department of Computer Science and Engineering, IIT Madras, Chennai - 600036
Administrative Unit: