Educational Services for RTL Design and Verification

Submitted by Anonymous on Mon, 2014-02-24 16:26

Service required for curriculum development in the areas of Bluespec RTL Design, Verification and FPGA Optimization

Reference: 
CSEN/2013/010/KAMA/SPLX
File: 
Tender RTL 010.pdf
Opening Date: 
24/02/14
Closing Date: 
07/03/14
Address: 
V. Kamakoti, Department of Computer Science and Engineering, IIT Madras, Chennai - 600036
Keywords: 
RTL;Bluespec;VLSI Design; VLSI Verification
Administrative Unit: 
Department of Computer Science and Engineering