Total Area of 4mm2 IC in TSMC 65 GP CMOS process

Submitted by smpur-icsr on Mon, 2021-10-18 15:48

Total Area of 4mm2 IC in TSMC 65 GP CMOS process

Reference: 
EE/ANI/2021/4MM2 TSMC65GPCMOS
File: 
ANNEXURE-III
CPP PROOF
Tender document
Opening Date: 
18/10/21
Closing Date: 
25/10/21
Address: 
Dr. Aniruddhan S, Department of Electrical Engineering IIT Madras, Sardar Patel Road, Chennai - 600 036
Keywords: 
Total Area of 4mm2 IC in TSMC 65 GP CMOS process
Administrative Unit: 
Department of Electrical Engineering