Two Quantities of 2mm x 1.04mm IC in TSMC 65 GP CMOS process

Submitted by smpur-icsr on Wed, 2021-05-19 16:16

Two Quantities of 2mm x 1.04mm IC in TSMC 65 GP CMOS process

Reference: 
EE/SAUR/2021/2MM TSMC65GPCMOS
File: 
Tender document
Annexure - III
CPP PROOF
Opening Date: 
19/05/21
Closing Date: 
28/05/21
Address: 
Dr. Saurabh Saxena, Department of Electrical Engineering IIT Madras, Sardar Patel Road, Chennai - 600 036
Keywords: 
Two Quantities of 2mm x 1.04mm IC in TSMC 65 GP CMOS process
Administrative Unit: 
Department of Electrical Engineering